The measured reaction time will be displayed on the LCD display. The Reaction Timer will then illuminate all eight of the individual LEDs of the Basys2 board and measure the length of time before the user presses the Start button again. When the Start button is pressed, the Reaction Timer will wait for a random length of time between 1 and 3 seconds while displaying “Wait for LEDs…” on the LCD display. On Reset, the Reaction timer will initially display an introduction message “Reaction Timer” on the connected LCD to the Basys2 Board.
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This lab focuses on designing a Reaction Timer that measures a user’s reaction time by counting the time elapsed between illuminating a set of LEDs and the pressing of a button by a user. Introduction This lab is an extension of the previous few labs because of the structural implementation of the top level module which involves the Clock Divider module and several concepts from the previous labs.
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The lab also familiarized us to assign FPGA pins, implement our FSM design and to load the design onto the FPGA board interfaced with a Pmod CLP 16x2 Character Display LCD. The lab familiarized us on how the one-procedure methods for states is easier compared to the two-procedure design method. We had to consider the button-bouncing problem in the Reaction timer design and how it affected our design logic. Lab report writing: 50-50 Abstract The final project enabled us to build a Reaction Timer by using the one-procedure method.In-lab testbench simulation and analysis: 50-50.In-lab module and testbench design: 50-50.Team 2: Richie Mean & Jeffy Biju CSEE 4270 Final Project: Reaction Timer Lab Report Due Date: NovemContributions